1. Field of the Invention
The present invention relates to a processing apparatus. More specifically, the invention relates to a fault tolerant system such as a logic operation unit that performs a series of operations using all or some of operation units mounted thereon.
2. Description of the Related Art
Recently, there have been not a few logic operation units, such as computers for controlling infrastructure, which operate on a 24-hour basis. These units are required at the minimum to process data without errors during operation. Under the circumstances, the fault tolerant technology is becoming more important than conventional.
The fault tolerant technology has conventionally been introduced chiefly into a storage system such as a memory. More specifically, the technology has been applied to a parity check system and an error correction circuit (ECC). At present, it is essential to introduce the tolerant technology into the storage system because the number of elements in the storage system is much larger than that in a logic circuit such as a control circuit and an operation unit and the availability of the storage system is higher than that of the control circuit.
In contrast, the introduction of the tolerant technology into the logic circuit has not been considered so significant because the number of elements is smaller, the availability is lower, and the mounting costs are higher than those in the storage system.
Paying attention to the process technology, the logic circuit decreases in size further to meet demands for higher packed density and higher operation speed. However, the logic circuits vary widely in their manufacturing process and thus difficult to manufacture with a robust circuit that secures such a large margin as conventional. In particular, the recent problem is a soft error due to minute particles. The probability of occurrence of the soft error increases, which cannot be ignored.
In order to make the operation speed higher than that of each of the logic circuits and increase the amount of data to be processed therein, the logic circuits are arranged in parallel. Unlike the prior art system, the recent system is implemented not by a high-speed, single processor using the leading-edge process and manufacturing technology, but by coupling inexpensive microprocessors, which are decreased in costs by miniaturization, in parallel or massively parallel. This system increases in the amount of hardware of the logic circuits and the possibility of a breakdown.
As described above, it becomes more important to secure the reliability of logic circuits that were not conventionally be considered so significant. A system capable of securing the reliability of an operation unit has already been known (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-040081).
However, as a demand for the reliability of logic circuits is growing, it becomes important to configure a system capable of not only reducing the amount of hardware but also lowering its costs and maintaining its security without degrading any functions.